Gate driver circuits drive currents which are provided to control terminals (gates) of power devices. Examples of power devices that use such gate driver circuits include power metal-oxide semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), gallium nitride (GaN) transistors, and silicon carbide (SiC) MOSFETs. The efficient use of power devices within practical applications requires that an appropriate drive current be provided by gate driver circuits to the power device gates.
Power devices perform most efficiently when they are fully on (e.g., saturated) or fully off (non-conducting). As a power device transitions between fully-on and fully-off states, the power device incurs switching losses that reduce efficiency. Switching losses may be minimized by limiting the transition time for a power device. This generally requires that a relatively large current be provided to a gate (control) terminal of a power device when turning the power device on, and that a large current be sunk from the gate (control) terminal when turning off the power device. High current levels quickly charge or discharge the gate capacitance of the power device, thereby limiting the time spent transitioning the power device between its fully-on and fully-off states. However, the gate drive current levels may not be increased without limit, as the power device is only capable of handling current below a certain level. Furthermore, generation of the drive current incurs its own losses, which must be traded off against the switch losses incurred during switch transitions.
A given power device typically has an optimal current gate drive level, and may have an acceptable range of current levels around the optimal level. The optimal current level and an associated acceptable range will vary from one power device to the next for the same power device design, due to process variations in manufacturing the power devices. For example, the channel width, channel length, gate capacitance, etc. vary across power devices on a given wafer and, potentially more significantly, for the power devices on different wafers. Due to these variations, it may be desirable to adjust the gate drive current level for one or more power devices in an application, at least if power efficiency is to be optimized.
Power devices are used in a variety of circuit applications. Common applications of power devices that require gate drivers include half-bridge and full-bridge circuits. (A full-bridge circuit is merely two half bridges configured in parallel, and will not be further discussed.) A half-bridge circuit includes a high-side and a low-side switch (power device) connected in series between a voltage source and a reference node, e.g., ground, and are connected to each other at a switching node. Half-bridge circuits are commonly used in a variety of switched mode power supplies, including buck converters, boost converters, isolated flyback converters, and resonant converters. The high and low-side switches are alternately switched, such that the high-side switch connects the voltage source to the switching node during a first conducting interval, and the low-side switch connects the switching node to the reference node during a second conducting interval. So as to avoid connecting the voltage source directly to the reference node, the switches should not conduct at the same time. This means that the first and second conducting intervals must be separated by a so-called “dead time,” during which neither switch conducts. The dead-time intervals should be minimized so that a high percentage of each switching cycle may be used for transferring power. Reducing the dead-time intervals may be achieved by appropriate setting of the gate driver current level such that the gate control voltage approximates a square wave as closely as feasible for the associated power device.
Gate driver circuitry and techniques that can set optimal or near-optimal current levels for driving the gates of power devices are desired.